/**
 * @brief Functions for setting and getting the state of the SPI lines.
 *
 * These need to be implemented by the user of this library.
 */
typedef struct {
    /*
     * Delay ns
     */
    void(*delay)(ms_ptr_t io_ctx, ms_uint32_t ns);

    /*
     * Return the state of the MISO line (zero/non-zero value)
     */
    ms_uint8_t (*get_miso)(ms_ptr_t io_ctx);

    /*
     * Set the state of the MOSI line (zero/non-zero value)
     */
    void (*set_mosi)(ms_ptr_t io_ctx, ms_uint8_t state);

    /*
     * Set the state of the SCK line (zero/non-zero value)
     */
    void (*set_sck)(ms_ptr_t io_ctx, ms_uint8_t state);

} const ms_spi_bitbang_io_t;

ms_err_t ms_spi_bitbang_bus_dev_create(const char *bus_name, const char *path, 
                                       ms_spi_bitbang_io_t *io, ms_ptr_t io_ctx);

#include "ms_config.h"
#include "ms_rtos.h"
#include "includes.h"
#include "spi/ms_drv_spi_bitdang.h"

/*
 * Set the state of the SCK line (zero/non-zero value)
 */
static void __spi_io_set_sck(ms_ptr_t io_ctx, ms_uint8_t state)
{
    if (state != 0) {
        gpio_bit_set(SPI_SCK_GPIO_PORT, SPI_SCK_GPIO_PIN);
    } else {
        gpio_bit_reset(SPI_SCK_GPIO_PORT, SPI_SCK_GPIO_PIN);
    }
}

/*
 * Return the state of the MISO line (zero/non-zero value)
 */
static ms_uint8_t __spi_io_get_miso(ms_ptr_t io_ctx)
{
    if (gpio_input_bit_get(SPI_MISO_GPIO_PORT, SPI_MISO_GPIO_PIN) == RESET) {
        return 0;
    } else {
        return 1;
    }
}

/*
 * Set the state of the MOSI line (zero/non-zero value)
 */
static void __spi_io_set_mosi(ms_ptr_t io_ctx, ms_uint8_t state)
{
    if (state != 0) {
        gpio_bit_set(SPI_MOSI_GPIO_PORT, SPI_MOSI_GPIO_PIN);
    } else {
        gpio_bit_reset(SPI_MOSI_GPIO_PORT, SPI_MOSI_GPIO_PIN);
    }
}

/*
 * Delay ns
 */
static void __spi_io_delay(ms_ptr_t io_ctx, ms_uint32_t ns)
{
    bsp_delay_us((ns + (1000 - 1)) / 1000);
}

/*
 * ms_spi_bitbang_io_t
 */
static ms_spi_bitbang_io_t __spi_io = {
    .set_sck  = __spi_io_set_sck,
    .set_mosi = __spi_io_set_mosi,
    .get_miso = __spi_io_get_miso,
    .delay    = __spi_io_delay,
};

/*
 * SPI GPIO initialization function
 */
void bsp_spi_emulator_init(const char *bus_name, const char *path)
{
    /* Enable all GPIO clock */
    SPI_ALL_GPIO_EN();

    /* Configure SCK (PB3) pin as push-pull output with pull-up */
    gpio_mode_set(SPI_SCK_GPIO_PORT, GPIO_MODE_OUTPUT, 
                  GPIO_PUPD_NONE, SPI_SCK_GPIO_PIN);
    gpio_output_options_set(SPI_SCK_GPIO_PORT, GPIO_OTYPE_PP, 
                            GPIO_OSPEED_50MHZ, SPI_SCK_GPIO_PIN);
    gpio_bit_set(SPI_SCK_GPIO_PORT, SPI_SCK_GPIO_PIN);

    /* Configure MISO (PB4) pin as push-pull output with pull-up */
    gpio_mode_set(SPI_MISO_GPIO_PORT, GPIO_MODE_OUTPUT, 
                  GPIO_PUPD_NONE, SPI_MISO_GPIO_PIN);
    gpio_output_options_set(SPI_MISO_GPIO_PORT, GPIO_OTYPE_PP, 
                            GPIO_OSPEED_50MHZ, SPI_MISO_GPIO_PIN);
    gpio_bit_set(SPI_MISO_GPIO_PORT, SPI_MISO_GPIO_PIN);

    /* Configure MOSI (PB5) pin as push-pull output with pull-up */
    gpio_mode_set(SPI_MOSI_GPIO_PORT, GPIO_MODE_OUTPUT, 
                  GPIO_PUPD_NONE, SPI_MOSI_GPIO_PIN);
    gpio_output_options_set(SPI_MOSI_GPIO_PORT, GPIO_OTYPE_PP, 
                            GPIO_OSPEED_50MHZ, SPI_MOSI_GPIO_PIN);
    gpio_bit_set(SPI_MOSI_GPIO_PORT, SPI_MOSI_GPIO_PIN);
	
    ms_spi_bitbang_bus_dev_create(bus_name, path, &__spi_io, MS_NULL);
}

#define __MS_IO
#include "ms_config.h"
#include "ms_rtos.h"
#include "ms_io_core.h"
#include <string.h>
#include "includes.h"

/*
 * Private info
 */
typedef struct {
    ms_uint8_t      channel;
    ms_spi_param_t  param;

    ms_handle_t     rx_complete_sem;
    char            rx_sem_name[__SPI_MAX_NAME_LEN];
    ms_handle_t     tx_complete_sem;
    char            tx_sem_name[__SPI_MAX_NAME_LEN];
} privinfo_t;

/*
 * @brief  transmit and receive
 */
static ms_ssize_t __sccb9001cxx_spi_bus_trans(ms_ptr_t bus_ctx, ms_spi_cs_func_t cs,
                                              const ms_spi_msg_t *msg, ms_size_t n_msg)
{
    int         i;
    privinfo_t *priv = bus_ctx;
    ms_err_t    err;

    for (i = 0; i < n_msg; i++, msg++) {

        /*
         * Fix 1 line TRANSMODE to receive data or transmit data
         */
        if (priv->param.direction == MS_SPI_DIRECTION_1LINE) {
            if (!!(msg->flags & MS_SPI_M_WRITE)) {
                priv->native_param.trans_mode = SPI_TRANSMODE_BDTRANSMIT;
            } else {
                priv->native_param.trans_mode = SPI_TRANSMODE_BDRECEIVE;
            }
            __sccb9001cxx_spi_bus_configure(priv, &priv->native_param);
        }

        /*
         * Assert CS before transfer
         */
        if ((msg->flags & MS_SPI_M_BEGIN) && (priv->param.nss == MS_SPI_NSS_SOFT)) {
            if (cs) {
                cs(MS_TRUE);
            }
        }

        /*
         * SPI transmit data with dma or polling
         */
        if (priv->hw_dma_en) {
            err = __sccb9001cxx_spi_transmit_receive_dma(priv, msg, MS_TIMEOUT_FOREVER);
        } else {
            err = __sccb9001cxx_spi_transmit_receive(priv, msg, MS_TIMEOUT_FOREVER);
        }

        /*
         * Deassert CS after transfer
         */
        if ((msg->flags & MS_SPI_M_END) && (priv->param.nss == MS_SPI_NSS_SOFT)) {
            if (cs) {
                cs(MS_FALSE);
            }
        }

        if (err != MS_ERR_NONE) {
            break;
        }
    }

    return  i;
}

/*
 * __sccb9001cxx_spi_bus_ioctl
 */
static int __sccb9001cxx_spi_bus_ioctl(ms_ptr_t bus_ctx, int cmd, ms_ptr_t arg)
{
    privinfo_t *priv = bus_ctx;
    ms_err_t    err;
    int         ret;

    switch (cmd) {
    case MS_SPI_CMD_GET_PARAM:
        if (ms_access_ok(arg, sizeof(ms_spi_param_t), MS_ACCESS_W)) {
            *(ms_spi_param_t *)arg = priv->param;
            ret = 0;
        } else {
            ms_thread_set_errno(EFAULT);
            ret = -1;
        }
        break;

    case MS_SPI_CMD_SET_PARAM:
        if (ms_access_ok(arg, sizeof(ms_spi_param_t), MS_ACCESS_R)) {
            priv->param = *(ms_spi_param_t *)arg;

            err = __sccb9001cxx_spi_bus_param_convert(&priv->param, &priv->native_param);
            if (err == MS_ERR_NONE) {
                __sccb9001cxx_spi_bus_configure(priv, &priv->native_param);
                ret = 0;

            } else {
                ms_thread_set_errno(EINVAL);
                ret = -1;
            }

        } else {
            ms_thread_set_errno(EFAULT);
            ret = -1;
        }
        break;

    default:
        ms_thread_set_errno(EINVAL);
        ret = -1;
        break;
    }

    return ret;
}

static ms_spi_bus_ops_t sccb9001cxx_spi_bus_ops = {
        .trans = __sccb9001cxx_spi_bus_trans,
        .ioctl = __sccb9001cxx_spi_bus_ioctl,
};

static privinfo_t spi_bus_privinfo[__SPI_MAX_CHANNEL_NUM] = {
    {
            .channel = 0,
            .base    = SPI0,
            .irq     = SPI0_IRQn,
    },
};

static ms_spi_bus_t spi_bus_info[__SPI_MAX_CHANNEL_NUM] = {
    {
        .nnode = {
            .name = "spi0",
        },
        .ops = &sccb9001cxx_spi_bus_ops,
        .ctx = &spi_bus_privinfo[0],
    },
};

/*
 * Create SPI device file
 */
ms_err_t sccb9001cxx_spi_bus_dev_create(const char *path, ms_uint32_t channel)
{
    bsp_dma_logic_id_t      tx_dma_id;
    bsp_dma_logic_id_t      rx_dma_id;
    sccb9001_spi_hw_info_t  hw_info;
    ms_spi_bus_t           *spi_bus;
    privinfo_t             *priv;
    ms_err_t                err;

    if (path == MS_NULL || channel >= __SPI_MAX_CHANNEL_NUM) {
        return MS_ERR;
    }

    spi_bus       = &spi_bus_info[channel];
    priv          = spi_bus->ctx;
    priv->channel = channel;

    sprintf(priv->rx_sem_name, "spi%d-rxsem", channel);
    if (ms_semb_create(priv->rx_sem_name, MS_FALSE, 
                       MS_WAIT_TYPE_PRIO, &priv->rx_complete_sem) != MS_ERR_NONE) {
        goto abort_exit;
    }

    sprintf(priv->tx_sem_name, "spi%d-txsem", channel);
    if (ms_semb_create(priv->tx_sem_name, MS_FALSE, 
                       MS_WAIT_TYPE_PRIO, &priv->tx_complete_sem) != MS_ERR_NONE) {
        goto abort_exit;
    }

    err = bsp_spi_low_level_init(channel, &hw_info);
    if (err == MS_ERR_NONE) {
        priv->base           = hw_info.spi_base;
        priv->irq            = hw_info.spi_irq;
        priv->hw_cs_en       = hw_info.hw_cs_en;
        priv->hw_dma_en      = hw_info.hw_dma_en;
        priv->tx_dma_base    = hw_info.tx_dma_base;
        priv->tx_dma_channel = hw_info.tx_dma_channel;
        priv->tx_dma_subperi = hw_info.tx_dma_subperi;
        priv->rx_dma_base    = hw_info.rx_dma_base;
        priv->rx_dma_channel = hw_info.rx_dma_channel;
        priv->rx_dma_subperi = hw_info.rx_dma_subperi;

        if (hw_info.hw_dma_en) {
            err = __SPI_TX_DMA_ID(&hw_info, &tx_dma_id);
            if (err == MS_ERR_NONE) {
                err = __SPI_RX_DMA_ID(&hw_info, &rx_dma_id);
            }

            if (err == MS_ERR_NONE) {
                priv->tx_dma_id         = tx_dma_id.dma_id;
                priv->tx_dma_channel_id = tx_dma_id.channel_id;
                priv->rx_dma_id         = rx_dma_id.dma_id;
                priv->rx_dma_channel_id = rx_dma_id.channel_id;
            } else {
                goto abort_exit;
            }
        }

        priv->param.baud_rate      = 400000;
        priv->param.mode           = MS_SPI_MODE_MASTER;
        priv->param.direction      = MS_SPI_DIRECTION_2LINES;
        priv->param.data_size      = MS_SPI_DATA_SIZE_8BIT;
        priv->param.frame_mode     = MS_SPI_CLK_POLARITY_HIGH | 
                                     MS_SPI_CLK_PHASE_2EDGE | MS_SPI_FIRST_BIT_MSB;
        priv->param.nss            = MS_SPI_NSS_SOFT;
        priv->param.crc_polynomial = 7;

        err = __sccb9001cxx_spi_bus_param_convert(&priv->param, &priv->native_param);
        if (err == MS_ERR_NONE) {
            __sccb9001cxx_spi_bus_configure(priv, &priv->native_param);

            err =  ms_spi_bus_register(spi_bus);
            if (err == MS_ERR_NONE) {
                err = ms_spi_bus_dev_create(path, spi_bus);
            }
        }
    }

    return err;

abort_exit:
    return MS_ERR;
}

typedef struct {
    ms_uint32_t     baud_rate;  	// Specifies the clock frequency.    
    ms_uint8_t      mode;       	// Specifies the SPI operating mode.        
    ms_uint8_t      direction;   	// Specifies the SPI Directional mode.      
    ms_uint8_t      data_size;    	// Specifies the SPI data size.            
    ms_uint16_t     frame_mode; 	// Specifies the frame mode.
    ms_uint8_t      nss;        	// whether the NSS signal is managed by hardware.
    ms_uint32_t     crc_polynomial; // the polynomial used for the CRC calculation. 
} ms_spi_param_t;

typedef struct {
    ms_uint16_t     flags;		// 传输控制参数
    ms_ptr_t        tx_buf;		// 发送缓冲区
    ms_ptr_t        rx_buf;		// 接收缓冲区
    ms_size_t       len;		// 缓冲区大小
} ms_spi_msg_t;

#define __MS_IO
#include "ms_kern.h"
#include "ms_io_core.h"
#include "ms_driver.h"
#include "ms_littlefs.h"
#include "ms_drv_nor_spi.h"

#include <string.h>
#include <ctype.h>

/**
 * @brief nor flash device driver.
 */

#define MS_RAWFLASH_DRV_NAME       "rawflash"

/*
 * NOR FLASH Chip Command
 */
typedef struct {
    ms_uint8_t  en_4byte_addr;                                          /* enable 4 bytes address mode  */
    ms_uint8_t  en_wr;                                                  /* enable write                 */
    ms_uint8_t  rd_sta_reg1;                                            /* read status register1        */
    ms_uint8_t  rd_sta_reg2;                                            /* read status register2        */
    ms_uint8_t  rd_sta_reg3;                                            /* read status register3        */
    ms_uint8_t  rd_id;                                                  /* read chip id                 */
    ms_uint8_t  rd_data;                                                /* read data                    */
    ms_uint8_t  wr_data;                                                /* write data                   */
    ms_uint8_t  wr_data2;                                               /* write data 2                 */
    ms_uint8_t  sector_erase;                                           /* erase sector                 */
} ms_chip_cmd;

/*
 * Private information of chip
 */
typedef struct {
    char              *chip_name;
    ms_uint32_t        id;
    ms_uint8_t         en_4byte_addr;

    ms_size_t          size;
    ms_size_t          sector_size;
    ms_size_t          page_size;

    const ms_chip_cmd *cmds;
} ms_chip_info;

/*
 * Provide to litterfs for data transmission
 */
typedef struct {
    const ms_chip_info *cur_chip_info;
    ms_spi_device_t     spi_dev;
} privinfo_t;

/*
 * nor flash infomation
 */
typedef struct {
    ms_io_device_t     dev;
    privinfo_t         priv;
} ms_nor_dev_t;

/*
 * Provide to litterfs for data transmission
 */
typedef struct {
    privinfo_t          *priv;
    ms_uint32_t          part_base;
    ms_size_t            part_size;
} partinfo_t;

/*
 * One to one correspondence with the command of operation chip
 */

#define CHIP_CMD_ID_W25Q  0
#define CHIP_CMD_ID_M25P  1
#define CHIP_CMD_ID_AT45D 2

const static ms_chip_cmd chip_cmd[] = {

    /*
     *  w25qxx, mx25xxx
     */
    {
        .en_4byte_addr = 0xB7,
        .en_wr         = 0x06,
        .rd_sta_reg1   = 0x05,
        .rd_sta_reg2   = 0x35,
        .rd_sta_reg3   = 0x15,
        .rd_id         = 0x9F,
        .rd_data       = 0x03,
        .wr_data       = 0x02,
        .sector_erase  = 0x20,
    },

    /*
     *  w25pxx
     */
    {
        .en_wr         = 0x06,
        .rd_sta_reg1   = 0x05,
        .rd_id         = 0x9F,
        .rd_data       = 0x03,
        .wr_data       = 0x02,
        .sector_erase  = 0xD8,
    },
    /*
     * at45dxxx
     */
    {
        .rd_sta_reg1   = 0xD7,
        .rd_id         = 0x9F,
        .rd_data       = 0x0B,
        .wr_data       = 0x82,
        .wr_data2      = 0x85,
        .sector_erase  = 0x50,
    },
};

/*
 * all chips information
 */
const static ms_chip_info all_chip_info[] = {
    /*
     * chip_name, id, en_4byte_addr, size. sector_size, page_size, cmds
     */
    {
        "gd25q32", 0xC84016, 0, 4 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "gd25q64", 0xC84017, 0, 8 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "gd25q127c", 0xC84018, 0, 16 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "gd25q257d", 0xC84019, 1, 32 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "gd25q256e", 0xC84019, 1, 32 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "w25q16",  0xef4015, 0, 2 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "w25q32",  0xef4016, 0, 4 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "w25q64",  0xef4017, 0, 8 * 1024 * 1024,  4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "w25q128", 0xef4018, 0, 16 * 1024 * 1024, 4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "w25q256", 0xef4019, 1, 32 * 1024 * 1024, 4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "m25p05",  0x202010, 0, 64 * 1024,        32 * 1024, 128, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p10",  0x202011, 0, 128 * 1024,       32 * 1024, 128, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p20",  0x202012, 0, 256 * 1024,       64 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p40",  0x202013, 0, 512 * 1024,       64 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p80",  0x202014, 0, 1* 1024 * 1024,   64 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p16",  0x202015, 0, 2 * 1024 * 1024,  64 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p32",  0x202016, 0, 4 * 1024 * 1024,  64 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p64",  0x202017, 0, 8 * 1024 * 1024,  64 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25p128", 0x202018, 0, 16 * 1024 * 1024, 256 * 1024, 256, &chip_cmd[CHIP_CMD_ID_M25P]
    },
    {
        "m25l51245g", 0xc2201a, 1, 64 * 1024 * 1024, 4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
    {
        "AT45DB021E", 0x1f2300, 0 , 2 * 1024 * 1024, 2 * 1024, 256, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DB041E", 0x1f2400, 0 , 4 * 1024 * 1024, 2 * 1024, 256, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DB081E", 0x1f2500, 0 , 8 * 1024 * 1024, 2 * 1024, 256, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DB161E", 0x1f2600, 0,  16 * 1024 * 1024, 4 * 1024, 512, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DQ161", 0x1f2600, 0,  16 * 1024 * 1024, 4 * 1024, 512, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DB321E", 0x1f2700, 0,  32 * 1024 * 1024, 4 * 1024, 512, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DQ321", 0x1f2701, 0,  32 * 1024 * 1024, 4 * 1024, 512, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "AT45DB641E", 0x1f2800, 0, 64 * 1024 * 1024, 2 * 1024, 256, &chip_cmd[CHIP_CMD_ID_AT45D]
    },
    {
        "MX25L25645G", 0XC22019, 0, 32 * 1024 * 1024, 4 * 1024, 256, &chip_cmd[CHIP_CMD_ID_W25Q]
    },
};

/**
 * @brief raw flash lock.
 */
static ms_handle_t  rawflash_lock;
#define __RAWFLASH_LOCK()     ms_mutex_lock(rawflash_lock, MS_TIMEOUT_FOREVER)
#define __RAWFLASH_UNLOCK()   ms_mutex_unlock(rawflash_lock);

/*
 * brief:   read norflash Status register
 * regno:   Register number
 * ret:     The value of the register
 */
static ms_uint8_t __norflash_read_sr(privinfo_t *priv, ms_uint8_t regno)
{
    ms_uint8_t   cmd;
    ms_uint8_t   dump;
    ms_uint8_t   rx;
    ms_spi_msg_t msgs[2];

    switch (regno)
    {
        case 1:
            cmd = priv->cur_chip_info->cmds->rd_sta_reg1;
            break;
        case 2:
            cmd = priv->cur_chip_info->cmds->rd_sta_reg2;
            break;
        case 3:
            cmd = priv->cur_chip_info->cmds->rd_sta_reg3;
            break;
        default:
            cmd = priv->cur_chip_info->cmds->rd_sta_reg1;
            break;
    }

    msgs[0].len    =  1;
    msgs[0].tx_buf = &cmd;
    msgs[0].rx_buf = &dump;
    msgs[0].flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

    dump = 0;
    msgs[1].len    =  1;
    msgs[1].tx_buf = &dump;
    msgs[1].rx_buf = &rx;
    msgs[1].flags  =  MS_SPI_M_TX_FIX | MS_SPI_M_READ | MS_SPI_M_END;

    if (ms_spi_device_trans(&priv->spi_dev, msgs, 2) != 2) {
        rx = 0;
    }

    return rx;
}

/*
 * wait free
 */
static void __norflash_wait_busy(privinfo_t *priv, ms_uint32_t delay_ms)
{
    while ((__norflash_read_sr(priv, 1) & 0x01) == 0x01) {
        if (delay_ms) {
            ms_thread_sleep_ms(delay_ms);
        }
    }
}

/*
 * enable write
 */
static void __norflash_write_enable(privinfo_t *priv)
{
    ms_uint8_t   dump;
    ms_spi_msg_t msg;

    msg.len    =  1;
    msg.rx_buf = &dump;
    msg.tx_buf = &priv->cur_chip_info->cmds->en_wr;
    msg.flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_ONCE;

    ms_spi_device_trans(&priv->spi_dev, &msg, 1);
}

/*
 * read chip id
 */
static ms_uint32_t __norflash_read_id(privinfo_t *priv)
{
    ms_uint32_t  chip_id = 0;
    ms_uint8_t   dump;
    ms_uint8_t   rx[3];
    ms_spi_msg_t msgs[2];

    msgs[0].len    =  1;
    msgs[0].tx_buf = &priv->cur_chip_info->cmds->rd_id;
    msgs[0].rx_buf = &dump;
    msgs[0].flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

    dump = 0;
    msgs[1].len    =  3;
    msgs[1].tx_buf = &dump;
    msgs[1].rx_buf =  rx;
    msgs[1].flags  =  MS_SPI_M_TX_FIX | MS_SPI_M_READ | MS_SPI_M_END;

    if (ms_spi_device_trans(&priv->spi_dev, msgs, 2) != 2) {
        chip_id = 0;
    } else {
        chip_id  = (ms_uint32_t)(rx[0] << 16);
        chip_id += (ms_uint32_t)(rx[1] << 8);
        chip_id += (ms_uint32_t)(rx[2] << 0);
    }

    return chip_id;
}


/*
 * brief:   read SPI FLASH, Start reading data of specified length at the specified address
 * buf:     Data storage area
 * addr:    Address to start reading
 * len:     Number of bytes to read
 */
static void __norflash_read(privinfo_t *priv, ms_ptr_t buf, ms_uint32_t addr, ms_size_t len)
{
    ms_uint8_t   dump;
    ms_uint8_t   tx[5];
    ms_spi_msg_t msgs[2];

    __RAWFLASH_LOCK();

    if (buf) {
        tx[0] = priv->cur_chip_info->cmds->rd_data;

        if (priv->cur_chip_info->en_4byte_addr == 0) {
            msgs[0].len = 4;
            tx[1]       = (ms_uint8_t)(addr >> 16);
            tx[2]       = (ms_uint8_t)(addr >> 8);
            tx[3]       = (ms_uint8_t)(addr);
        } else {
            msgs[0].len = 5;
            tx[1]       = (ms_uint8_t)(addr >> 24);
            tx[2]       = (ms_uint8_t)(addr >> 16);
            tx[3]       = (ms_uint8_t)(addr >> 8);
            tx[4]       = (ms_uint8_t)(addr);
        }

        msgs[0].tx_buf  =  tx;
        msgs[0].rx_buf  = &dump;
        msgs[0].flags   =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

        dump = 0;
        msgs[1].len     =  len;
        msgs[1].tx_buf  = &dump;
        msgs[1].rx_buf  =  buf;
        msgs[1].flags   =  MS_SPI_M_TX_FIX | MS_SPI_M_READ | MS_SPI_M_END;

        ms_spi_device_trans(&priv->spi_dev, msgs, 2);
    }

    __RAWFLASH_UNLOCK();
}

/*
 * brief:  SPI writes data in a page, Write up to 256 bytes of data at the specified address
 * buf:    Data storage area
 * addr:   Address to start writing Address to start writing
 * len:    The number of bytes to write, which should not exceed the remaining
 *         bytes of the page!!!
 */
static void __norflash_write_page(privinfo_t *priv, ms_const_ptr_t buf, ms_uint32_t addr, ms_size_t len)
{
    ms_uint8_t   dump;
    ms_spi_msg_t msgs[2];
    ms_uint8_t   tx[5];

    if (buf) {

        __norflash_write_enable(priv);
        __norflash_wait_busy(priv, 0);

        tx[0] = priv->cur_chip_info->cmds->wr_data;

        if (priv->cur_chip_info->en_4byte_addr == 0) {
            msgs[0].len = 4;
            tx[1]       = (ms_uint8_t)(addr >> 16);
            tx[2]       = (ms_uint8_t)(addr >> 8);
            tx[3]       = (ms_uint8_t)(addr);
        } else {
            msgs[0].len = 5;
            tx[1]       = (ms_uint8_t)(addr >> 24);
            tx[2]       = (ms_uint8_t)(addr >> 16);
            tx[3]       = (ms_uint8_t)(addr >> 8);
            tx[4]       = (ms_uint8_t)(addr);
        }

        msgs[0].tx_buf  =  tx;
        msgs[0].rx_buf  = &dump;
        msgs[0].flags   =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

        dump = 0;
        msgs[1].len     =  len;
        msgs[1].tx_buf  =  buf;
        msgs[1].rx_buf  = &dump;
        msgs[1].flags   =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_END;

        ms_spi_device_trans(&priv->spi_dev, msgs, 2);
        __norflash_wait_busy(priv, 0);

    }
}

/*
 *  brief:  Write SPI flash,  Start to write the data of the specified length at the specified
 *          address. The function has erase operation!
 *  buf:    Data storage area
 *  addr:   Address to start writing
 *  len:    Number of bytes to write
 */
static void __norflash_write(privinfo_t *priv, ms_const_ptr_t buf, ms_uint32_t addr, ms_size_t len)
{
    ms_uint32_t len_wr_able;

    __RAWFLASH_LOCK();

    while (len) {
        len_wr_able = priv->cur_chip_info->page_size - (addr % priv->cur_chip_info->page_size);
        if (len_wr_able > len) {
            len_wr_able = len;
        }

        __norflash_write_page(priv, buf, addr, len_wr_able);

        addr += len_wr_able;
        buf  += len_wr_able;
        len  -= len_wr_able;
    }

    __RAWFLASH_UNLOCK();
}

/*
 * brief:   erase a sector, at least spend 150ms
 * addr:    address
 */
static void __norflash_erase(privinfo_t *priv, ms_uint32_t addr)
{
    ms_uint8_t   dump;
    ms_spi_msg_t msg;
    ms_size_t    len;
    ms_uint8_t   tx[5];

    __RAWFLASH_LOCK();

    tx[0]  = priv->cur_chip_info->cmds->sector_erase;

    if (priv->cur_chip_info->en_4byte_addr == 0) {
        len   = 4;
        tx[1] = (ms_uint8_t)(addr >> 16);
        tx[2] = (ms_uint8_t)(addr >> 8);
        tx[3] = (ms_uint8_t)(addr);
    } else {
        len   = 5;
        tx[1] = (ms_uint8_t)(addr >> 24);
        tx[2] = (ms_uint8_t)(addr >> 16);
        tx[3] = (ms_uint8_t)(addr >> 8);
        tx[4] = (ms_uint8_t)(addr);
    }

    msg.len    =  len;
    msg.rx_buf = &dump;
    msg.tx_buf =  tx;
    msg.flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_ONCE;

    __norflash_write_enable(priv);
    __norflash_wait_busy(priv, 0);
    ms_spi_device_trans(&priv->spi_dev, &msg, 1);
    __norflash_wait_busy(priv, 1);

    __RAWFLASH_UNLOCK();
}

/*
 * Read a region in a block. Negative error codes are propogated to the user.
 */
static int __norflash_block_read(const struct lfs_config *c, lfs_block_t block,
                                 lfs_off_t off, void *buffer, lfs_size_t size)
{
    ms_uint32_t  addr = block * c->block_size + off;

    __norflash_read(c->context, buffer, addr, size);

    return LFS_ERR_OK;
}

/*
 * Program a region in a block. The block must have previously been erased. Negative error codes are
 * propogated to the user.May return LFS_ERR_CORRUPT if the block should be considered bad.
 */
static int __norflash_block_prog(const struct lfs_config *c, lfs_block_t block,
                                 lfs_off_t off, const void *buffer, lfs_size_t size)
{
    ms_uint32_t addr = block * c->block_size + off;

    __norflash_write(c->context, buffer, addr, size);

    return LFS_ERR_OK;
}

/*
 * Erase a block. A block must be erased before being programmed.
 * The state of an erased block is undefined. Negative error codes are propogated to the user.
 * May return LFS_ERR_CORRUPT if the block should be considered bad.
 */
static int __norflash_block_erase(const struct lfs_config *c, lfs_block_t block)
{
    ms_uint32_t addr = block * c->block_size;

    __norflash_erase(c->context, addr);

    return LFS_ERR_OK;
}

/*
 * brief:   read norflash Status register
 * regno:   Register number
 * ret:     The value of the register
 */
static ms_uint16_t __at45d_norflash_read_sr(privinfo_t *priv)
{
    ms_uint8_t   cmd;
    ms_uint8_t   dump;
    ms_uint8_t   rx[2];
    ms_uint16_t  status = 0;
    ms_spi_msg_t msgs[2];

    cmd = priv->cur_chip_info->cmds->rd_sta_reg1;

    msgs[0].len    =  1;
    msgs[0].tx_buf = &cmd;
    msgs[0].rx_buf = &dump;
    msgs[0].flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

    dump = 0;
    msgs[1].len    =  2;
    msgs[1].tx_buf = &dump;
    msgs[1].rx_buf = &rx;
    msgs[1].flags  =  MS_SPI_M_TX_FIX | MS_SPI_M_READ | MS_SPI_M_END;

    if (ms_spi_device_trans(&priv->spi_dev, msgs, 2) == 2) {
        status |= rx[0] << 8;
        status |= rx[1];
    }

    return status;
}

/*
 * wait free
 */
static void __at45d_norflash_wait_busy(privinfo_t *priv, ms_uint32_t delay_ms)
{
    while ((__at45d_norflash_read_sr(priv) & 0x80) == 0x00) {
        if (delay_ms) {
            ms_thread_sleep_ms(delay_ms);
        }
    }
}

/*
 * Sync the state of the underlying block device. Negative error codes
 * are propogated to the user.
 */
static int __norflash_block_sync(const struct lfs_config *c)
{
    return LFS_ERR_OK;
}

#define AT45DXX_DEBUG_LOG       0
#define AT45DXX_DUMMY           0x00
/*
 * Read a region in a block. Negative error codes are propogated to the user.
 */
static int __at45d_norflash_block_read(const struct lfs_config *c, lfs_block_t block,
                                       lfs_off_t off, void *buffer, lfs_size_t size)
{
    ms_uint32_t  addr = block * c->block_size + off;
    privinfo_t  *priv = c->context;

    ms_uint8_t   dump;
    ms_uint8_t   tx[5];
    ms_spi_msg_t msgs[2];

    if (buffer) {
        tx[0]   = priv->cur_chip_info->cmds->rd_data;
        tx[1]   = (ms_uint8_t)(addr >> 16);
        tx[2]   = (ms_uint8_t)(addr >> 8);
        tx[3]   = (ms_uint8_t)(addr);
        tx[4]   = AT45DXX_DUMMY;

        msgs[0].len     =  5;
        msgs[0].tx_buf  =  tx;
        msgs[0].rx_buf  = &dump;
        msgs[0].flags   =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

        dump = 0;
        msgs[1].len     =  size;
        msgs[1].tx_buf  = &dump;
        msgs[1].rx_buf  =  buffer;
        msgs[1].flags   =  MS_SPI_M_TX_FIX | MS_SPI_M_READ | MS_SPI_M_END;

        ms_spi_device_trans(&priv->spi_dev, msgs, 2);

#if AT45DXX_DEBUG_LOG > 0
        ms_printk(MS_PK_ERR, "read block[%d] off[%d] addr[%#x] len[%d]:\r\n", block, off, addr, size);
        int i;
        for (i = 0; i < size; i++) {
            ms_printk(MS_PK_ERR, "%x ", ((ms_uint8_t*)buffer)[i]);
        }
        ms_printk(MS_PK_ERR, "finish\r\n");
#endif
    }

    return LFS_ERR_OK;
}

/*
 * brief:  SPI writes data in a page, Write up to 256 bytes of data at the specified address
 * buf:    Data storage area
 * addr:   Address to start writing Address to start writing
 * len:    The number of bytes to write, which should not exceed the remaining
 *         bytes of the page!!!
 */
static void __at45d_norflash_write_page(privinfo_t *priv, ms_const_ptr_t buf, ms_uint32_t addr, ms_size_t len)
{
    static ms_uint8_t   _at45_buffer;
    ms_uint8_t          dump;
    ms_spi_msg_t        msgs[2];
    ms_uint8_t          tx[5];

    if (buf) {

        tx[0] = _at45_buffer ? priv->cur_chip_info->cmds->wr_data :
                               priv->cur_chip_info->cmds->wr_data2;
        _at45_buffer = !_at45_buffer;

        tx[1] = (ms_uint8_t)(addr >> 16);
        tx[2] = (ms_uint8_t)(addr >> 8);
        tx[3] = (ms_uint8_t)(addr);

        msgs[0].len = 4;
        msgs[0].tx_buf  =  tx;
        msgs[0].rx_buf  = &dump;
        msgs[0].flags   =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_BEGIN;

        dump = 0;
        msgs[1].len     =  len;
        msgs[1].tx_buf  =  buf;
        msgs[1].rx_buf  = &dump;
        msgs[1].flags   =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_END;

        ms_spi_device_trans(&priv->spi_dev, msgs, 2);
        if (_at45_buffer)
            __at45d_norflash_wait_busy(priv, 0);
    }
}

/*
 * Program a region in a block. The block must have previously been erased. Negative error codes are
 * propogated to the user.May return LFS_ERR_CORRUPT if the block should be considered bad.
 */
static int __at45d_norflash_block_prog(const struct lfs_config *c, lfs_block_t block,
                                       lfs_off_t off, const void *buffer, lfs_size_t size)
{
    ms_uint32_t  addr = block * c->block_size + off;
    privinfo_t  *priv = c->context;

    ms_uint32_t len_wr_able;

    __at45d_norflash_wait_busy(priv, 0);
    while (size) {
        len_wr_able = priv->cur_chip_info->page_size - (addr % priv->cur_chip_info->page_size);
        if (len_wr_able > size) {
            len_wr_able = size;
        }

        __at45d_norflash_write_page(priv, buffer, addr, len_wr_able);

#if AT45DXX_DEBUG_LOG > 0
        ms_printk(MS_PK_ERR, "write block[%d] off[%d] addr[%#x] len[%d]:\r\n", block, off, addr, len_wr_able);
        int i;
        for (i = 0; i < len_wr_able; i++) {
            ms_printk(MS_PK_ERR, "%x ", ((ms_uint8_t*)buffer)[i]);
        }
        ms_printk(MS_PK_ERR, "finish\r\n");
#endif

        addr += len_wr_able;
        buffer  += len_wr_able;
        size  -= len_wr_able;
    }
    __at45d_norflash_wait_busy(priv, 0);

    return LFS_ERR_OK;
}

/*
 * Erase a block. A block must be erased before being programmed.
 * The state of an erased block is undefined. Negative error codes are propogated to the user.
 * May return LFS_ERR_CORRUPT if the block should be considered bad.
 */
static int __at45d_norflash_block_erase(const struct lfs_config *c, lfs_block_t block)
{
    ms_uint8_t   dump;
    ms_uint32_t  addr = block * c->block_size;
    privinfo_t  *priv = c->context;

    ms_spi_msg_t msg;
    ms_uint8_t   tx[4];

    tx[0]  = priv->cur_chip_info->cmds->sector_erase;
    tx[1] = (ms_uint8_t)(addr >> 16);
    tx[2] = (ms_uint8_t)(addr >> 8);
    tx[3] = (ms_uint8_t)(addr);

    msg.len    =  4;
    msg.rx_buf = &dump;
    msg.tx_buf =  tx;
    msg.flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_ONCE;

    __at45d_norflash_wait_busy(priv, 0);
    ms_spi_device_trans(&priv->spi_dev, &msg, 1);
    __at45d_norflash_wait_busy(priv, 1);

#if AT45DXX_DEBUG_LOG > 0
    ms_printk(MS_PK_ERR, "erase block[%d] addr[%#x]\r\n", block, addr);
#endif

    return LFS_ERR_OK;
}

/*
 * Sync the state of the underlying block device. Negative error codes
 * are propogated to the user.
 */
static int __at45d_norflash_block_sync(const struct lfs_config *c)
{
    return LFS_ERR_OK;
}

/*
 * Confirm Chip ID
 */
static ms_err_t __norflash_confirm_chips_id(privinfo_t *priv)
{
    ms_uint32_t chip_id;
    ms_err_t    err;

    chip_id = __norflash_read_id(priv);
    if (chip_id == priv->cur_chip_info->id) {
        err = MS_ERR_NONE;
    } else {
        err = MS_ERR_IO;
    }

    return err;
}

/*
 * configure address mode
 */
static void __norflash_cfg_addr_mode(privinfo_t *priv)
{
    ms_uint8_t   dump;
    ms_spi_msg_t msg;
    ms_uint8_t   temp;

    if (priv->cur_chip_info->en_4byte_addr != 0) {
        temp = __norflash_read_sr(priv, 3);
        if ((temp & 0X01) == 0) {
            msg.len    =  1;
            msg.rx_buf = &dump;
            msg.tx_buf = &priv->cur_chip_info->cmds->en_4byte_addr;
            msg.flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_ONCE;
            ms_spi_device_trans(&priv->spi_dev, &msg, 1);
        }
    }
}

/*
 * at45d series chip could configure buffer and page size
 * to ensure compatibility of file system, setting buffer and page size to
 * "power of 2" binary page size
 */
static void __norflash_cfg_page_size(privinfo_t *priv)
{
    ms_uint8_t   dump;
    ms_spi_msg_t msg;
    ms_uint8_t   tx[4];

#define AT45DXX_ID_MASK     0xFFE000
#define AT45DXX_SERIES_ID   0x1F2000
#define AT45DXX_BINARY_PAGE 0x3D2A80A6
    if ((priv->cur_chip_info->id & AT45DXX_ID_MASK) == AT45DXX_SERIES_ID) {
        if ((__at45d_norflash_read_sr(priv) & 0x100) == 0x0) {
            tx[0] = (ms_uint8_t)(AT45DXX_BINARY_PAGE >> 24);
            tx[1] = (ms_uint8_t)(AT45DXX_BINARY_PAGE >> 16);
            tx[2] = (ms_uint8_t)(AT45DXX_BINARY_PAGE >> 8);
            tx[3] = (ms_uint8_t)(AT45DXX_BINARY_PAGE);

            msg.len    =  4;
            msg.rx_buf = &dump;
            msg.tx_buf =  tx;
            msg.flags  =  MS_SPI_M_RX_FIX | MS_SPI_M_WRITE | MS_SPI_M_ONCE;
            ms_spi_device_trans(&priv->spi_dev, &msg, 1);
        }
    }
}

static const ms_chip_info *__norflash_is_supported(const char *dev_name)
{
    ms_ssize_t         i;
    ms_ssize_t         j;
    char               chip_name_low[20];
    char               dev_name_low[20];

    for (i = 0; i < MS_ARRAY_SIZE(all_chip_info); i++) {
        bzero(chip_name_low, sizeof(chip_name_low));
        bzero(dev_name_low, sizeof(dev_name_low));

        for (j = 0; all_chip_info[i].chip_name[j]; j++) {
            chip_name_low[j] = tolower(all_chip_info[i].chip_name[j]);
        }

        for (j = 0; dev_name[j]; j++) {
            dev_name_low[j] = tolower(dev_name[j]);
        }

        if (strcmp(chip_name_low, dev_name_low) == 0) {
            return  &all_chip_info[i];
        }
    }

    return  MS_NULL;
}

/*
 * create norflash device
 */
ms_err_t ms_nor_dev_create(ms_nor_port_t *norflash_port)
{
    ms_err_t             err = MS_ERR;
    const ms_chip_info  *chip_info = MS_NULL;
    ms_nor_dev_t        *dev;
    struct lfs_config   *lfs_cfg;

    if ((norflash_port->mount_path    != MS_NULL) &&
        (norflash_port->bus_name      != MS_NULL) &&
        (norflash_port->dev_path      != MS_NULL) &&
        (norflash_port->dev_name      != MS_NULL) &&
        (norflash_port->gpio_init     != MS_NULL) &&
        (norflash_port->cs            != MS_NULL)) {
        chip_info = __norflash_is_supported(norflash_port->dev_name);
        if (chip_info != MS_NULL) {
            dev     = ms_kmalloc(sizeof(ms_nor_dev_t));
            lfs_cfg = ms_kmalloc(sizeof(struct lfs_config));
            if (dev != MS_NULL && lfs_cfg != MS_NULL) {
                privinfo_t *priv = &dev->priv;

                bzero(dev, sizeof(ms_nor_dev_t));
                bzero(lfs_cfg, sizeof(struct lfs_config));

                priv->cur_chip_info      =  chip_info;
                priv->spi_dev.cs         =  norflash_port->cs;
                priv->spi_dev.nnode.name =  norflash_port->dev_path;
                err = ms_spi_device_attach(&priv->spi_dev, norflash_port->bus_name);
                if (err == MS_ERR_NONE) {
                    err = ms_spi_device_ioctl(&priv->spi_dev, MS_SPI_CMD_SET_PARAM, &norflash_port->spi_param);
                    if (err == MS_ERR_NONE) {
                        norflash_port->gpio_init();
                        /*
                         * confirm id is right
                         */
                        err = __norflash_confirm_chips_id(priv);
                        if (err == MS_ERR_NONE) {
                            __norflash_cfg_addr_mode(priv);
                            __norflash_cfg_page_size(priv);

                            lfs_cfg->context        = &dev->priv;
                            lfs_cfg->read_size      =  1U;
                            lfs_cfg->prog_size      =  priv->cur_chip_info->page_size;
                            lfs_cfg->block_size     =  priv->cur_chip_info->sector_size;
                            lfs_cfg->block_count    =  priv->cur_chip_info->size / priv->cur_chip_info->sector_size;
                            lfs_cfg->cache_size     =  priv->cur_chip_info->page_size;
                            lfs_cfg->block_cycles   =  500U;
                            lfs_cfg->lookahead_size =  8U * ((priv->cur_chip_info->size / priv->cur_chip_info->sector_size + 63U) / 64U);
                            if ((priv->cur_chip_info->id & AT45DXX_ID_MASK) == AT45DXX_SERIES_ID) {
                                lfs_cfg->read           =  __at45d_norflash_block_read,
                                lfs_cfg->prog           =  __at45d_norflash_block_prog,
                                lfs_cfg->erase          =  __at45d_norflash_block_erase,
                                lfs_cfg->sync           =  __at45d_norflash_block_sync;
                            }else {
                                lfs_cfg->read           =  __norflash_block_read,
                                lfs_cfg->prog           =  __norflash_block_prog,
                                lfs_cfg->erase          =  __norflash_block_erase,
                                lfs_cfg->sync           =  __norflash_block_sync;
                            }
                            err = ms_io_device_register(&dev->dev, norflash_port->dev_path, "ms_null", lfs_cfg);
                            if (err == MS_ERR_NONE) {
                                err = ms_io_mount(norflash_port->mount_path,
                                                  norflash_port->dev_path, MS_LITTLEFS_NAME, MS_NULL);
                                if (err != MS_ERR_NONE) {
                                    ms_io_device_unregister(&dev->dev);
                                }
                            }
                        }
                    }
                    if (err != MS_ERR_NONE) {
                        ms_spi_device_detach(&priv->spi_dev, norflash_port->bus_name);
                    }
                }

                if (err != MS_ERR_NONE) {
                    (void)ms_kfree(dev);
                    (void)ms_kfree(lfs_cfg);
                }
            } else {
                err = MS_ERR_KERN_HEAP_NO_MEM;

                if (dev != MS_NULL) {
                    (void)ms_kfree(dev);
                }

                if (lfs_cfg != MS_NULL) {
                    (void)ms_kfree(lfs_cfg);
                }
            }
        }
    } else {
        err = MS_ERR_ARG_NULL_PTR;
    }

    if (err == MS_ERR_NONE) {
        err = ms_mutex_create("rawflash_lock", MS_WAIT_TYPE_PRIO, &rawflash_lock);
        if (err != MS_ERR_NONE) {
            err = MS_ERR_KERN_HEAP_NO_MEM;
        }
    }

    return err;
}

/*
 * Open device
 */
static int __norflash_raw_open(ms_ptr_t ctx, ms_io_file_t *file, int oflag, ms_mode_t mode)
{
    ms_atomic_inc(MS_IO_DEV_REF(file));

    return 0;
}

/*
 * Close device
 */
static int __norflash_raw_close(ms_ptr_t ctx, ms_io_file_t *file)
{
    ms_atomic_dec(MS_IO_DEV_REF(file));

    return 0;
}

/*
 * Read or write one message data from rawflash
 */
static int __norflash_raw_rw_msg(partinfo_t *part, ms_rawflash_msg_t *msg, ms_uint8_t access_mode)
{
    ms_size_t rawflash_size = part->part_size;
    ms_size_t block_size;
    int ret;

    if (msg->memaddr >= rawflash_size ||
        (msg->memaddr + msg->len) > (part->part_base + rawflash_size)) {
        ms_thread_set_errno(EINVAL);
        ret = -1;

    } else {
        ms_uint8_t *pbuf = msg->buf;
        ms_uint32_t addr = part->part_base + msg->memaddr;
        ms_uint32_t len;
        ms_uint32_t next_addr;
        ms_uint32_t already_len = 0; /* the length of already rw */

        ret = 0;
        block_size = part->priv->cur_chip_info->sector_size;

        while (already_len < msg->len) {
            next_addr = (addr + block_size) / block_size * block_size;

            len = next_addr - addr;
            if ((already_len + len) > msg->len) {
                len = msg->len - already_len;
            }

            if (access_mode == MS_ACCESS_R) {
                __norflash_read(part->priv, pbuf, addr, len);

            } else {
                __norflash_write(part->priv, pbuf, addr, len);
            }

            addr = next_addr;
            pbuf += len;
            already_len += len;
        }
    }

    return ret;
}

static ms_ssize_t  __norflash_raw_rw(partinfo_t *part, ms_rawflash_msg_t *msg, ms_size_t len, ms_uint8_t access_mode)
{
    ms_ssize_t ret;
    ms_uint8_t buf_access_mode;

    if (access_mode == MS_ACCESS_W) {
        buf_access_mode = MS_ACCESS_R;
    } else {
        buf_access_mode = MS_ACCESS_W;
    }

    if (len % sizeof(ms_rawflash_msg_t) == 0) {
        ms_uint32_t n_msg = len / sizeof(ms_rawflash_msg_t);
        ms_uint32_t i;

        for (i = 0; i < n_msg; i++) {
            /*
             * access permission check
             */
            if (!ms_access_ok((void*)msg->buf, msg->len, buf_access_mode)) {
                ms_thread_set_errno(EFAULT);
                break;
            }

            /*
             * process reading or writing
             */
            if (__norflash_raw_rw_msg(part, msg, access_mode) != 0) {
                break;
            }

            msg++;
        }

        if (i == n_msg) {
            ret = len;
        } else {
            ret = -1;
        }

    } else {
        ms_thread_set_errno(EFAULT);
        ret = -1;
    }

    return ret;
}


/*
 * Read device
 */
static ms_ssize_t __norflash_raw_read(ms_ptr_t ctx, ms_io_file_t *file, ms_ptr_t buf, ms_size_t len)
{
    return __norflash_raw_rw((partinfo_t *)ctx, (ms_rawflash_msg_t *)buf, len, MS_ACCESS_R);
}

/*
 * Write device
 */
static ms_ssize_t __norflash_raw_write(ms_ptr_t ctx, ms_io_file_t *file, ms_const_ptr_t buf, ms_size_t len)
{
    return __norflash_raw_rw((partinfo_t *)ctx, (ms_rawflash_msg_t *)buf, len, MS_ACCESS_W);
}

/*
 * Control device
 */
static int __norflash_raw_ioctl(ms_ptr_t ctx, ms_io_file_t *file, int cmd, void *arg)
{
    partinfo_t *part = (partinfo_t *)ctx;
    privinfo_t *priv = part->priv;
    int ret;

    switch (cmd) {
    case MS_RAWFLASH_CMD_GET_GEOMETRY:
        if (ms_access_ok(arg, sizeof(ms_rawflash_geometry_t), MS_ACCESS_W)) {
            ms_rawflash_geometry_t *geometry = (ms_rawflash_geometry_t *)arg;
            geometry->sector_size  = priv->cur_chip_info->sector_size;
            geometry->sector_count = part->part_size/priv->cur_chip_info->sector_size;
            ret = 0;

        } else {
            ms_thread_set_errno(EFAULT);
            ret = -1;
        }
        break;

    case MS_RAWFLASH_CMD_ERASE_SECTOR:
        if (ms_access_ok(arg, sizeof(ms_rawflash_erase_t), MS_ACCESS_R)) {
            ms_uint32_t i;
            ms_uint32_t block_count = part->part_size/priv->cur_chip_info->sector_size;
            ms_uint32_t block_base  = part->part_base/priv->cur_chip_info->sector_size;
            ms_rawflash_erase_t *erase_msg = (ms_rawflash_erase_t *)arg;
            for (i = 0; i < erase_msg->count; i++) {
                if (erase_msg->sector + i < block_count) {
                    __norflash_erase(priv, (block_base + erase_msg->sector + i) * priv->cur_chip_info->sector_size);
                } else {
                    break;
                }
            }
            ret = 0;

        } else {
            ms_thread_set_errno(EFAULT);
            ret = -1;
        }
        break;

    default:
        ms_thread_set_errno(EINVAL);
        ret = -1;
        break;
    }

    return ret;
}

/*
 * Device operating function set
 */
static ms_io_driver_ops_t ms_nor_raw_drv_ops = {
        .type   = MS_IO_DRV_TYPE_CHR,
        .open   = __norflash_raw_open,
        .close  = __norflash_raw_close,
        .write  = __norflash_raw_write,
        .read   = __norflash_raw_read,
        .ioctl  = __norflash_raw_ioctl,
};


/*
 * Device driver
 */
static ms_io_driver_t __norflash_raw_drv = {
    .nnode = {
        .name = MS_RAWFLASH_DRV_NAME,
    },
    .ops = &ms_nor_raw_drv_ops,
};

/*
 * Register rawflash device driver
 */
ms_err_t ms_nor_rawflash_drv_register(void)
{
    return ms_io_driver_register(&__norflash_raw_drv);
}
/*
 * create norflash device
 */
ms_err_t ms_nor_dev_create_with_parts(ms_nor_port_t *norflash_port)
{
    ms_err_t           err = MS_ERR;
    ms_ssize_t         i, chip_index;
    ms_nor_dev_t      *dev;

    ms_uint32_t        part_num = 0;
    ms_nor_partattr_t *parts_attr;
    ms_uint32_t        hw_init = 0;
    ms_uint32_t        part_offt = 0;
    ms_uint32_t        part_size = 0;

    if ( (norflash_port->parts_get == MS_NULL) &&
         (norflash_port->bus_name  == MS_NULL) &&
         (norflash_port->dev_name  == MS_NULL) &&
         (norflash_port->gpio_init == MS_NULL) &&
         (norflash_port->cs        == MS_NULL)) {

        return MS_ERR;
    }

    for (chip_index = 0; chip_index < MS_ARRAY_SIZE(all_chip_info); chip_index++) {
        if (strcmp(all_chip_info[chip_index].chip_name, norflash_port->dev_name) == 0) {
            break;
        }
    }

    if (chip_index >= MS_ARRAY_SIZE(all_chip_info)) {
        return MS_ERR;
    }

    err = ms_mutex_create("rawflash_lock", MS_WAIT_TYPE_PRIO, &rawflash_lock);
    if (err != MS_ERR_NONE) {
        ms_printk(MS_PK_ERR, "create rawflash_lock fail!\n");
        goto error_exit;
    }

    part_num = norflash_port->parts_get(&parts_attr);

    for (i = 0; i < part_num; i++) {
        dev = ms_kmalloc(sizeof(ms_nor_dev_t));
        if (dev == MS_NULL ) {
            goto error_exit;
        }

        bzero(dev, sizeof(ms_nor_dev_t));

        privinfo_t *priv = &dev->priv;
        priv->cur_chip_info      = &all_chip_info[chip_index];
        priv->spi_dev.cs         = norflash_port->cs;
        err = ms_spi_device_attach(&priv->spi_dev, norflash_port->bus_name);
        if (err != MS_ERR_NONE) {
            goto error_exit;
        }

        if (hw_init == 0) {
            err = ms_spi_device_ioctl(&priv->spi_dev, MS_SPI_CMD_SET_PARAM, &norflash_port->spi_param);
            if (err != MS_ERR_NONE) {
                goto error_exit;
            }

            norflash_port->gpio_init();
            err = __norflash_confirm_chips_id(priv);
            if (err != MS_ERR_NONE) {
                goto error_exit;
            }
            __norflash_cfg_addr_mode(priv);
            hw_init = 1;
        }

        part_size = priv->cur_chip_info->size * parts_attr[i].size_percent/100;

        if (parts_attr[i].is_rawflash) {

            partinfo_t *part_info = ms_kmalloc(sizeof(partinfo_t));
            if (part_info == MS_NULL ) {
                (void)ms_kfree(dev);
                goto error_exit;
            }

            part_info->priv      = priv;
            part_info->part_size = part_size;
            part_info->part_base = part_offt;

            err = ms_io_device_register(&dev->dev, parts_attr[i].dev_path, MS_RAWFLASH_DRV_NAME, part_info);
            if (err != MS_ERR_NONE) {
                (void)ms_kfree(dev);
                (void)ms_kfree(part_info);
                goto error_exit;
            }

        } else {
            struct lfs_config *lfs_cfg = ms_kmalloc(sizeof(struct lfs_config));
            if (lfs_cfg == MS_NULL ) {
                (void)ms_kfree(dev);
                goto error_exit;
            }
            bzero(lfs_cfg, sizeof(struct lfs_config));
            lfs_cfg->context        = &dev->priv;
            lfs_cfg->read_size      =  1U;
            lfs_cfg->prog_size      =  priv->cur_chip_info->page_size;
            lfs_cfg->block_size     =  priv->cur_chip_info->sector_size;
            lfs_cfg->block_count    =  part_size/ priv->cur_chip_info->sector_size;
            lfs_cfg->cache_size     =  priv->cur_chip_info->page_size;
            lfs_cfg->block_cycles   =  500U;
            lfs_cfg->lookahead_size =  8U * ((lfs_cfg->block_count + 63U) / 64U);
            lfs_cfg->read           =  __norflash_block_read;
            lfs_cfg->prog           =  __norflash_block_prog;
            lfs_cfg->erase          =  __norflash_block_erase;
            lfs_cfg->sync           =  __norflash_block_sync;
            err = ms_io_device_register(&dev->dev, parts_attr[i].dev_path, "ms_null", lfs_cfg);
            if (err != MS_ERR_NONE) {
                (void)ms_kfree(dev);
                (void)ms_kfree(lfs_cfg);
                goto error_exit;
            }
            err = ms_io_mount(parts_attr[i].mount_path,
                              parts_attr[i].dev_path, MS_LITTLEFS_NAME, MS_NULL);
            if (err != MS_ERR_NONE) {
                ms_io_device_unregister(&dev->dev);
                (void)ms_kfree(dev);
                (void)ms_kfree(lfs_cfg);
                goto error_exit;
            }
        }
        part_offt += part_size;
    }

    return err;

error_exit:
     ms_printk(MS_PK_ERR, "ms_nor_dev_create_with_parts error %d.\n", err);
    return err;
}