x86

[root@sylixos:/root]# help x86            
show x86 cpu information.
x86 [cpuid | cputop | mps | bios | ioint | loint | acpi]
[root@sylixos:/root]# 

[root@sylixos:/root]# x86

X86 CPU probe report

      vendorId: GenuineIntel
     signature: 0x506E3
   featuresEbx: 0x100800
   featuresEcx: 0x77FAFBBF
   featuresEdx: 0xBFEBFBFF
featuresEcxExt: 0x121
featuresEdxExt: 0x2C100000
      cacheEax: 0x76036301
      cacheEbx: 0xF0B6FF
      cacheEcx: 0x0
      cacheEdx: 0xC30000
    maxFuncEax: 0x16
 maxFuncEaxExt: 0x80000008

CPU info:
    Intel(R) Core(TM) i5-6400 CPU @ 2.70GHz
    model=0xE/5  stepping=3  family=6/0
    Number of processors: 16
    Local APIC id: 0

CPU features:
    ( X )  FPU on chip
    ( X )  Virtual 8086 mode enhancement
    ( X )  Debugging extensions
    ( X )  Page size extension
    ( X )  Time stamp counter
    ( X )  RDMSR and WRMSR support
    ( X )  Physical address extensions
    ( X )  Machine check exception
    ( X )  CMPXCHG8 inst
    ( X )  APIC on chip
    ( X )  Fast system calls
    ( X )  MTRR
    ( X )  PTE global bit
    ( X )  Machine check architecture
    ( X )  Cond. move/cmp. inst
    ( X )  Page attribute table
    ( X )  36 bit page size extension
    (   )  Processor serial number
    ( X )  CLFLUSH inst supported
    ( X )  Debug Store
    ( X )  ACPI registers in MSR space supported
    ( X )  MMX technology supported
    ( X )  Fast FP save and restore

    ( X )  SSE supported
    ( X )  SSE2 supported
    ( X )  Self Snoop supported
    ( X )  Hyper-Threading Technology/Core Multi-Processing supported
    ( X )  Thermal Monitor supported
    ( X )  Pending break enable
    ( X )  SSE3 supported
    ( X )  PCLMULDQ inst supported
    ( X )  64-bit debug store supported
    ( X )  MONITOR/MWAIT inst supported
    ( X )  CPL qualified debug store
    ( X )  VT Technology
    (   )  Safer mode extensions supported
    ( X )  Enhanced Speedstep Technology
    ( X )  Thermal Monitor 2 supported
    ( X )  SSSE3 supported
    (   )  L1 Context ID supported
    ( X )  IA32_DEBUG_INTERFACE_MSR supported
    ( X )  FMA Extensions Using XMM state supported
    ( X )  CMPXCHG16B inst supported
    ( X )  xTPR Update Control supported
    ( X )  Performance and Debug capability
    ( X )  ASID-PCID supported
    (   )  Direct Cache Access supported
    ( X )  SSE4.1 supported
    ( X )  SSE4.2 supported
    ( X )  x2APIC feature supported
    ( X )  MOVBE inst supported
    ( X )  POPCNT inst supported
    ( X )  TSC-deadline Timer supported
    ( X )  AES inst supported
    ( X )  XSAVE/XRSTOR States supported
    (   )  OS-Enabled Extended State management supported
    ( X )  AVX instr extensions supported
    ( X )  Float16 instructions supported
    ( X )  Read Random Number instructions supported
    (   )  SYSCALL/SYSRET inst supported
    ( X )  Execute Disable supported
    ( X )  1 GB Page Size Support supported
    ( X )  RDTSCP instruction and IA32_TSC_AUX_MSR supported
    ( X )  Intel 64 Arch extensions supported
    ( X )  LAHF/SAHF inst supported
    ( X )  Advanced Bit Manipulation supported

Deterministic Cache Parameters:
    L1 Data cache size 0x8000
        self initializing cache level: 1
        fully associative cache level: 0
        max threads sharing cache: 2
        num reserved APIC IDs: 8
        system coherency line size: 64
        physical line partitions: 1
        ways of associativity: 8
        number of sets: 64
        WBINDV/INDBV behavior on lower levels: 0
        inclusive to lower levels: 0
        uses complex function to index: 0
    L1 Instruction cache size 0x8000
        self initializing cache level: 1
        fully associative cache level: 0
        max threads sharing cache: 2
        num reserved APIC IDs: 8
        system coherency line size: 64
        physical line partitions: 1
        ways of associativity: 8
        number of sets: 64

 number of sets: 64
        WBINDV/INDBV behavior on lower levels: 0
        inclusive to lower levels: 0
        uses complex function to index: 0
    L2 Unified cache size 0x40000
        self initializing cache level: 1
        fully associative cache level: 0
        max threads sharing cache: 2
        num reserved APIC IDs: 8
        system coherency line size: 64
        physical line partitions: 1
        ways of associativity: 4
        number of sets: 1024
        WBINDV/INDBV behavior on lower levels: 0
        inclusive to lower levels: 0
        uses complex function to index: 0
    L3 Unified cache size 0x600000
        self initializing cache level: 1
        fully associative cache level: 0
        max threads sharing cache: 16
        num reserved APIC IDs: 8
        system coherency line size: 64
        physical line partitions: 1
        ways of associativity: 12
        number of sets: 8192
        WBINDV/INDBV behavior on lower levels: 0
        inclusive to lower levels: 1
        uses complex function to index: 1

MONITOR/MWAIT Parameters:
    smallest line size: 64 bytes
    largest line size: 64 bytes
    num C0 sub-states supported: 0
    num C1 sub-states supported: 2
    num C2 sub-states supported: 1
    num C3/6 sub-states supported: 2
    num C4/7 sub-states supported: 4
    ( X )  MONTIOR/MWAIT extension supported
    ( X )  interrupt break-events for MWAIT supported

Digital Thermal Sensor and Power Management Parameters:
    number of interrupt thresholds: 2
    ( X )  digital thermal sensor capability

  ( X )  interrupt break-events for MWAIT supported

Digital Thermal Sensor and Power Management Parameters:
    number of interrupt thresholds: 2
    ( X )  digital thermal sensor capability
    ( X )  Turbo Boost technology
    ( X )  Invariant Apic Timer
    ( X )  Power Limit Notification at Corei Level
    ( X )  Fine Grained Clock Modulation
    ( X )  Package Thermal Interrupt and Status support
    ( X )  hardware coordination feedback capability
    (   )  ACNT2 Capability
    ( X )  Energy Efficient Policy support

Performance Monitor Features:
    PerfMon version: 4
    ncounters per processor: 8
    nbits per counter: 48
    nevents per processor: 7
    ( X )  core cycles supported
    ( X )  instructions retired supported
    ( X )  reference cycles supported
    ( X )  last level cache references supported
    ( X )  last level cache misses supported
    ( X )  branch instructions retired supported
    ( X )  branch mispredicts retired supported

x2APIC Features / Processor Topology:
    Thread level topology:
        number of logical processors: 1
        extended APIC ID: 0
        bits to shift right for APIC ID: 1
    Core level topology:
        number of logical processors: 4
        extended APIC ID: 0
        bits to shift right for APIC ID: 4
    Package level topology:
        number of logical processors: 0
        extended APIC ID: 0
        bits to shift right for APIC ID: 0

Processor Extended State Enumeration (XSAVE):
    XFEATURE_ENABLED_MASK valid bitfield lower 32: 0x0000001f
    XFEATURE_ENABLED_MASK valid bitfield upper 32: 0x00000000
    max size required by XFEATURE_ENABLED_MASK: 576 bytes
    max size of XSAVE/XRESTORE save area: 1088 bytes

Cache Features:
    Data TLB: 4 KB Pages, 4-way set associative, 64 entries
    Instruction TLB: 4 KB Pages, 4-way set associative, 32 entries
    64-byte Prefetching

Extended L2 Cache Features:
    L2 cache line size: 64 bytes
    L2 cache size: 256 kbytes
    L2 cache associativity: 8-Way

Advanced Power Management:
    ( X )  TSC Invariance Available

Virtual and Physical Address Sizes:
    Physical address size: 39 bits
    Virtual address size: 48 bits